Multi-objective Optimization Approach for VLSI Implementation of FIR Filter

This paper présents a new approach for multi-objective optimization of area-delay-power simultaneously for VLSI implementation of digital finite impulse response filter. It is based on use of concept of multiple constant multiplication approach with partial product sharing and coefficient reuse in multiplier module and /or digit serial architecture in adder module design along with fixed point arithmetic. Designs are synthesized using Synopsys Design Compiler in 90 nm & 45 nm process technology. The synthesis results shows that proposed approach provide a good multi-objective optimization technique for digital FIR filter compared to other previous findings published in last decade.